Condor Currents

Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed - Hackaday** (google_riscv) --- *Sponsored by LimitLess AI*

OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization

## Episode Summary In this episode, we cover: - **OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization** (arXiv) - **TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing** (arXiv) - **Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)** (semiengineering) - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) --- *Sponsored by LimitLess AI*

How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum

## Episode Summary In this episode, we cover: - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) - **AI designs complete RISC-V CPU core in just 12 hours - MSN** (google_riscv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) - **Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost - Hackster.io** (google_riscv) --- *Sponsored by LimitLess AI*

Enhancing Instruction Prefetching via Cache and TLB Management

## Episode Summary In this episode, we cover: - **Enhancing Instruction Prefetching via Cache and TLB Management** (arXiv) - **ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC)** (semiengineering) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_riscv) - **CacheMind turns chip tuning into a conversation, exposing hidden cache failures and lifting processor performance - Tech Xplore** (google_arch) --- *Sponsored by LimitLess AI*

SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software

## Episode Summary In this episode, we cover: - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) --- *Sponsored by LimitLess AI*