[051] Industry briefing - EUV The Focal Point

[051] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. High-NA EUV infrastructure is moving from plans into physical installation as the first ASML EXE:5200 components reach Albany NanoTech. This episode examines why scanner power alone does not determine useful output: workforce retention, mask control, pellicle transmission, customer commitments, and research access increasingly shape EUV economics. Key takeaways - The first ASML TWINSCAN EXE:5200 components have begun arriving at Albany NanoTech, with first light targeted later in 2026 and research operations expected in early 2027. - Intel and Fortinet will collaborate on the Security Processor 6, but no process node, wafer volume, or EUV usage was disclosed. - ASML plans a €20,000 conditional retention grant for eligible employees who remain from 2027 through 2030. - Micron signed automotive Strategic Customer Agreements with seven major ecosystem partners to improve long-term supply, pricing, and technology visibility. - The 2026 EUVL and Source Workshop proceedings highlight rising mask-related variability, High-NA DRAM co-optimization, and higher-power EUV source development. - Lintec reports approximately 90% transmittance and up to 66-fold durability improvement for a carbon-nanotube pellicle under specified test conditions. - A 90%-transmitting pellicle leaves about 81% after two passes, while 95% leaves about 90%, illustrating why small transmission gains can materially affect dose and throughput. - This was a light week for new scanner shipment totals, and Intel’s manufacturing node for the Fortinet collaboration remains unclear. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light to pattern advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — A higher-resolution EUV platform using 0.55 numerical aperture optics. Low Numerical Aperture (Low-NA) EUV — The established 0.33 numerical aperture EUV platform used in high-volume manufacturing. Pellicle — A thin membrane that protects a photomask from particles while transmitting exposure light. Reticle — The reflective EUV photomask carrying the circuit pattern projected onto a wafer. Dynamic Random-Access Memory (DRAM) — Volatile memory used in computing systems and as the base technology for high-bandwidth memory. Application-Specific Integrated Circuit (ASIC) — A chip designed for a defined function rather than general-purpose computing. First light — The first successful generation and operation of EUV light in an installed scanner.

[050] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. High-NA EUV has moved into a shipping logic product, with Intel and ASML qualifying selected Panther Lake layers on the EXE platform. ASML also raised its 2026 outlook and outlined major Low-NA and DUV capacity increases, showing that the next lithography era will be based on coexistence rather than immediate replacement. Key takeaways: - Intel Foundry is shipping a subset of Panther Lake products with selected Intel 18A layers dual-qualified on High-NA EUV. - ASML says yields on the High-NA-qualified layers match its established NXE Low-NA platform. - Intel is using High-NA selectively rather than replacing the full Intel 18A lithography flow. - ASML reported Q2 net sales of €9.3 billion, a 54.0% gross margin, and €2.9 billion net income. - ASML raised its 2026 sales outlook to €43–45 billion. - ASML plans to increase its approximately 65-system 2026 Low-NA EUV capacity by 30% for 2027. - SK Hynix completed a $26.5 billion U.S. ADR offering intended partly for fabs and equipment including EUV scanners. - Micron’s Hiroshima expansion targets equipment installation from the second half of 2028 and supports future EUV-enabled DRAM and HBM capacity. - High-NA adoption is likely to remain layer-selective until its cost-per-good-layer advantage is proven across more products. Glossary: Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for advanced semiconductor patterning. High Numerical Aperture (High-NA) EUV — ASML’s newer EUV platform with higher optical resolution than conventional EUV. Low-NA EUV — The established 0.33-NA EUV platform used in current high-volume logic and memory production. Intel 18A — Intel’s advanced process node used for Panther Lake processors. Dual qualification — Approval of two process or equipment routes to manufacture the same layer or product. NXE — ASML’s established Low-NA EUV scanner family. EXE — ASML’s High-NA EUV scanner family. American Depositary Receipt (ADR) — A U.S.-traded security representing shares in a foreign company. Dynamic Random-Access Memory (DRAM) — Volatile memory used as working memory in computing systems. High Bandwidth Memory (HBM) — Stacked DRAM optimized for very high data bandwidth in AI and high-performance computing.

[049] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode is a light week for new EUV scanner shipment numbers, but a strong week for capacity signals. South Korea moved from capital pledges to execution pressure, Samsung and TSMC showed how roadmap credibility now depends on design ecosystem readiness, and IBM’s nanostack work sharpened the question of what High-NA EUV must prove before production insertion. Key takeaways - No new official ASML EUV shipment count or High-NA production insertion milestone surfaced this week. - South Korea’s president pushed officials to accelerate chip and AI projects, emphasizing permits, land, power, and water as capacity bottlenecks. - Reuters reported expected investments of about 400 trillion won each from Samsung and SK hynix in southwest chip sites, plus 81 trillion won for a Chungcheong packaging cluster. - SK hynix’s Cheongju plan points to 100 trillion won of investment, including 80 trillion won for M17 NAND and 20 trillion won for P&T7 advanced packaging and test. - Samsung reaffirmed SF1.4 volume production for 2029 and SF1.4+ for 2030, while highlighting DTCO as a major contributor to SF2-to-SF2P gains. - Anthropic’s reported exploratory talks with Samsung on 2nm and advanced packaging remain unconfirmed but show AI companies seeking foundry optionality. - Socionext plans a September 2026 tape-out of a compute chiplet on TSMC A14, making A14 ecosystem readiness more concrete. - Nvidia’s China AI chip position is under pressure from Huawei and local suppliers, while China remains blocked from ASML EUV systems. - IBM’s nanostack announcement is research, not production, but it reinforces the value of early High-NA EUV learning at Albany. - Reported TSMC price increases, Apple product-cost pressure, and Broadcom’s Apple deal all point to scarcity being converted into pricing power and long-term contracts. Glossary Extreme Ultraviolet (EUV) — 13.5-nanometer lithography used for critical layers in leading-edge semiconductor manufacturing. High Numerical Aperture (High-NA) EUV — ASML’s next-generation EUV platform with higher resolution and a more demanding process ecosystem. Low Numerical Aperture (Low-NA) EUV — The current mainstream EUV platform used in high-volume manufacturing. Design Technology Co-Optimization (DTCO) — Joint optimization of chip design rules and manufacturing processes to improve power, performance, area, and yield. High Bandwidth Memory (HBM) — Stacked DRAM used beside AI accelerators to deliver very high memory bandwidth. Dynamic Random-Access Memory (DRAM) — Volatile memory used in servers, PCs, phones, and HBM stacks. NAND — Non-volatile flash memory used for storage in devices and data centers. Tape-out — The point when a chip design is finalized and sent for manufacturing masks and fab processing. Advanced packaging — Integration technologies that connect logic, memory, and chiplets into high-performance systems. Option value — The strategic value of learning early so companies can choose among technologies before production decisions are locked.

[048] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV as part of a broader manufacturing system rather than a standalone scanner story. South Korea’s cluster plans, Micron’s record quarter, SK Hynix’s proposed U.S. listing, Dutch pushback on export controls, ASML’s photonics work with TNO, and xLight’s light-source ambitions all point to the same theme: future lithography capacity is being financed and managed like strategic infrastructure. Key takeaways: - South Korea is preparing a new southwest semiconductor hub, with local reports suggesting investments could exceed 1,000 trillion won over several years. - The expected South Korean support package is infrastructure-heavy: power, water, land, workforce training, transport, and housing all matter for EUV-ready capacity. - Micron reported record fiscal Q3 revenue of $41.46 billion and said data-center revenue exceeded $25 billion in the quarter. - Micron has signed 16 strategic customer agreements and expects memory tightness to persist beyond calendar 2027. - Micron projects fiscal 2026 capex of about $27 billion and expects higher quarterly capex in fiscal 2027, with construction capex driving more than half the year-over-year increase. - SK Hynix plans to raise up to 45.45 trillion won, or about $29.4 billion, through a U.S. American Depositary Receipt listing. - Dutch officials are pushing back against the MATCH Act because it could force allies into U.S.-style China export controls and affect DUV servicing. - ASML and TNO will use DUV and I-line lithography in a new Eindhoven pilot line for six-inch indium phosphide photonic chips. - The xLight $350 million fundraising item remains reported rather than officially announced; the official anchor is the June 2 U.S. CHIPS Act award. - This week’s focus is a mixed-fleet view of lithography: EUV carries the densest layers, but DUV still carries much of scale, yield, reliability, and cost. Glossary: Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for the most critical layers in advanced logic and memory. High Numerical Aperture (High-NA) — Next-generation EUV optics with higher resolution potential, but higher cost and integration complexity. Deep Ultraviolet (DUV) — Lithography using longer wavelengths such as 193 nanometers and 248 nanometers, still essential for many advanced-node layers. Dynamic Random-Access Memory (DRAM) — Volatile memory used across servers, PCs, mobile devices, and high-bandwidth memory stacks. High Bandwidth Memory (HBM) — Stacked DRAM optimized for very high data bandwidth near AI accelerators and graphics processors. American Depositary Receipt (ADR) — A U.S.-traded certificate representing shares of a foreign company. Free-electron laser — A light source using accelerated electrons; xLight is developing this approach as an alternative EUV source. Indium phosphide (InP) — A compound semiconductor material used for active photonic functions such as lasers and modulators. Strategic customer agreement — A longer-term commercial agreement intended to improve supply visibility, pricing durability, or capacity commitment.

[047] Industry briefing - EUV The Focal Point

Take the survey on Spotify!  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV less as a scanner-capacity headline and more as a manufacturing translation engine. The focus is the new 300-millimeter 2D-material transistor work from imec, ASML, and TSMC, plus Intel’s 18A-P risk-production milestone, ASML’s denial of EUV shipments to China, and fresh HBM4E sampling pressure from SK hynix. Key takeaways: - imec, ASML, and TSMC demonstrated complementary 2D-material nFETs and pFETs on a 300-millimeter wafer at 50-nanometer contacted poly pitch. - The 2D-material result used single-patterning EUV and reported 94 percent operational transistors, moving the work closer to manufacturable process exploration. - Intel 18A-P entered risk production with claims of 9 percent higher performance at the same power or 18 percent lower power at the same performance versus Intel 18A. - Intel’s VLSI update also highlighted thermal, via-resistance, CFET, GaN-on-silicon, and ruthenium-interconnect research as part of a longer scaling stack. - ASML denied that it has ever shipped an EUV machine, or EUV-specific components or modules, to China. - SK hynix shipped samples of 12-layer HBM4E to major customers, claiming up to 16 gigabits per second per pin and more than 20 percent power-efficiency improvement. - Intel’s appointment of Seok-Hee Lee to lead foundry packaging reinforces that lithography, memory integration, and advanced packaging are now tightly linked. - The EUVL and Source Workshop framed the longer roadmap around High-NA, hyper-NA, sources, materials, metrology, k1 reduction, and sub-13.5-nanometer lithography. Glossary: Extreme Ultraviolet (EUV) lithography — Lithography using 13.5-nanometer light to pattern advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation with higher optical numerical aperture for finer patterning. Contacted poly pitch (CPP) — A transistor scaling metric combining gate and source/drain contact dimensions. Two-dimensional transition metal dichalcogenides (2D TMDs) — Atomically thin channel materials such as MoS2, WS2, and WSe2. nFET and pFET — Negative-type and positive-type field-effect transistors used together in CMOS logic. Risk production — Early manufacturing phase used to validate process maturity before full high-volume ramp. High Bandwidth Memory 4E (HBM4E) — A next-generation stacked DRAM technology aimed at high-throughput AI systems. Complementary Field-Effect Transistor (CFET) — A vertically stacked transistor architecture that may extend logic scaling beyond gate-all-around devices.