EUV The Focal Point

[047] Industry briefing - EUV The Focal Point

Take the survey on Spotify!  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV less as a scanner-capacity headline and more as a manufacturing translation engine. The focus is the new 300-millimeter 2D-material transistor work from imec, ASML, and TSMC, plus Intel’s 18A-P risk-production milestone, ASML’s denial of EUV shipments to China, and fresh HBM4E sampling pressure from SK hynix. Key takeaways: - imec, ASML, and TSMC demonstrated complementary 2D-material nFETs and pFETs on a 300-millimeter wafer at 50-nanometer contacted poly pitch. - The 2D-material result used single-patterning EUV and reported 94 percent operational transistors, moving the work closer to manufacturable process exploration. - Intel 18A-P entered risk production with claims of 9 percent higher performance at the same power or 18 percent lower power at the same performance versus Intel 18A. - Intel’s VLSI update also highlighted thermal, via-resistance, CFET, GaN-on-silicon, and ruthenium-interconnect research as part of a longer scaling stack. - ASML denied that it has ever shipped an EUV machine, or EUV-specific components or modules, to China. - SK hynix shipped samples of 12-layer HBM4E to major customers, claiming up to 16 gigabits per second per pin and more than 20 percent power-efficiency improvement. - Intel’s appointment of Seok-Hee Lee to lead foundry packaging reinforces that lithography, memory integration, and advanced packaging are now tightly linked. - The EUVL and Source Workshop framed the longer roadmap around High-NA, hyper-NA, sources, materials, metrology, k1 reduction, and sub-13.5-nanometer lithography. Glossary: Extreme Ultraviolet (EUV) lithography — Lithography using 13.5-nanometer light to pattern advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation with higher optical numerical aperture for finer patterning. Contacted poly pitch (CPP) — A transistor scaling metric combining gate and source/drain contact dimensions. Two-dimensional transition metal dichalcogenides (2D TMDs) — Atomically thin channel materials such as MoS2, WS2, and WSe2. nFET and pFET — Negative-type and positive-type field-effect transistors used together in CMOS logic. Risk production — Early manufacturing phase used to validate process maturity before full high-volume ramp. High Bandwidth Memory 4E (HBM4E) — A next-generation stacked DRAM technology aimed at high-throughput AI systems. Complementary Field-Effect Transistor (CFET) — A vertically stacked transistor architecture that may extend logic scaling beyond gate-all-around devices.

[046] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode treats EUV capacity as a system problem rather than a scanner-count problem. The main thread runs from Rapidus funding and TeraFab signaling to ASML’s policy stance and new research on source efficiency. Key takeaways: - Rapidus completed an additional 150 billion yen government-backed funding round, bringing stated capital and legal capital surplus to 424.95 billion yen. - Rapidus also signed an MoU with the United Kingdom Semiconductor Centre, adding an international collaboration marker to its 2-nanometer roadmap. - Elon Musk’s TeraFab plan was discussed in connection with ASML’s internal technology conference, but no scanner count, node mix, or production timeline has been disclosed. - ASML’s Christophe Fouquet supported demand-driven European technology policy but warned against excessive Commission steering of strategic projects. - Cadence and Intel Foundry expanded DTCO collaboration for Intel 14A, reinforcing that High-NA readiness depends on design enablement as well as optics. - TSMC’s recent comments underline that AI-driven chip demand is constrained by talent, water, infrastructure, and operational sequencing, not only capex. - New EUV source-efficiency papers point to 2-micron laser-driver concepts and conversion-efficiency gains as a possible future productivity lever. - ASML’s AI-native engineering message links scanner productivity to software, diagnostics, defect detection, and service-time reduction. Glossary: Extreme Ultraviolet (EUV) — 13.5-nanometer lithography used for critical layers in advanced logic and memory. High Numerical Aperture (High-NA) — Next-generation EUV optics with higher resolution but more complex cost, mask, and process integration requirements. Design Technology Co-Optimization (DTCO) — Joint optimization of process technology and chip design rules to improve manufacturability and performance. Process Design Kit (PDK) — Foundry-provided files, models, and rules that let designers build chips for a specific process. Conversion efficiency — The fraction of laser energy converted into usable EUV light in the source. Laser-produced plasma — EUV source method in which laser pulses strike tin to generate 13.5-nanometer radiation. TeraFab — Proposed large-scale semiconductor manufacturing project associated with SpaceX, Tesla, and Intel discussions. IIM — Rapidus’ Innovative Integration for Manufacturing site in Chitose, Hokkaido. Source power — EUV light output available for wafer exposure, a key input to throughput and dose margin.

[045] Deep Dive Topic - Decodes imec's new logic innovations

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser This episode decodes imec's new logic innovation roadmap and explains why future scaling is no longer just about smaller transistors. We walk through the real physical metrics behind node names, the shift from FinFETs to nanosheets and CFETs, the role of High NA EUV, backside power delivery, CMOS 2.0, and active interposers. The focus is on the engineering trade-offs that make the roadmap technically credible, difficult, and important. Key takeaways - Node names are roadmap labels, not literal feature sizes. - Real scaling is better understood through contacted poly pitch, cell height, and metal pitch. - Gate-all-around nanosheets improve channel control and give designers a new drive-current versus area trade-off. - Forksheets may extend the nanosheet era, while CFETs promise tighter logic density through vertical transistor stacking. - High NA EUV improves imaging resolution but requires a new optical, mechanical, mask, and process ecosystem. - Backside power delivery attacks routing congestion and voltage loss by moving power wiring to the wafer backside. - CMOS 2.0 reframes scaling as a three-dimensional system-partitioning problem. - Active interposers could bring memory, photonics, capacitance, and voltage regulation closer to compute. - The future logic roadmap depends on co-optimizing devices, lithography, interconnect, power, packaging, and design tools. Glossary Contacted poly pitch: A physical spacing metric related to the distance between neighboring transistor gates in a standard logic cell. Cell height: The vertical size of a standard logic cell, often expressed in routing tracks. Reducing it improves density but constrains wiring and power resources. Metal pitch: The center-to-center distance between neighboring metal interconnect wires. It strongly affects wiring density and signal delay. FinFET: A fin-shaped field-effect transistor in which the gate controls multiple sides of a raised silicon channel. Gate-all-around transistor: A transistor architecture where the gate surrounds the channel on all sides for stronger electrostatic control. Nanosheet transistor: A gate-all-around transistor using stacked horizontal sheet-like channels. CFET: Complementary field-effect transistor. A future transistor architecture that vertically stacks n-type and p-type devices to reduce standard-cell footprint. High NA EUV: High numerical aperture extreme ultraviolet lithography. A next-generation EUV platform intended to print smaller features with improved resolution. Backside power delivery: A chip architecture that routes power from the wafer backside rather than through the frontside signal wiring stack. CMOS 2.0: Imec's concept for partitioning a system-on-chip into optimized functional tiers connected by dense 3D interconnects. Source list Always Be Curious, “Decoding imec's new industry roadmap for Logic innovation” — https://alwaysbecurious.substack.com/p/decoding-imecs-new-industry-roadmap

[044] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV lithography as a coordination problem rather than a single-tool problem. Korea’s approval reform, TSMC’s High-NA cost caution, SK hynix’s wafer-capacity plan, and Rapidus’s fresh government-backed funding all point to the same theme: the industry is trying to turn scarce exposure capacity into usable output faster. The focus topic connects scanner economics with regulation, memory, bonding, research speed, and system-level workarounds. Key takeaways: - South Korea plans to shorten EUV equipment import inspection and approval from 34 days to as few as nine days. - The Korean reform could cut overseas pressure and leak-test fees by about 5 billion won per EUV tool. - TSMC says it has purchased High-NA EUV tools for R&D but does not currently need them for production because the cost remains high. - SK hynix aims to double wafer capacity over the next five years while still expecting memory bottlenecks to persist into 2030. - Rapidus completed an additional 150 billion yen funding round from Japan’s Information-Technology Promotion Agency. - Intel says its 14A PDK 0.5 is available and that 14A PDK 0.9 is targeted for external customers in October. - Imec and EV Group demonstrated wafer-to-wafer hybrid bonding at a 200-nanometer copper pad pitch with post-bond overlay below 40 nanometers. - The University of Texas at Austin described a tabletop EUV and volumetric 3D patterning approach aimed at speeding research experiments, not replacing production scanners. - No new official ASML scanner shipment or throughput announcement was found this week; the ASML share buyback notice was financial housekeeping rather than a capacity update. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5-nanometer light to pattern critical layers in advanced chips. High Numerical Aperture (High-NA) EUV — next-generation EUV optics with higher resolution but higher cost and integration complexity. Low Numerical Aperture (Low-NA) EUV — today’s production EUV platform used widely for leading-edge logic and advanced memory. Process Design Kit (PDK) — the design-rule and model package customers need to begin designing chips for a foundry process. High Bandwidth Memory (HBM) — stacked DRAM used near AI processors to provide very high memory bandwidth. Dynamic Random-Access Memory (DRAM) — volatile memory technology used in servers, PCs, phones, and HBM stacks. Hybrid bonding — direct wafer or die bonding that creates dense vertical electrical connections for advanced packaging. Post-bond overlay — alignment accuracy after two wafers or dies are bonded. Cost per good die — the economic metric combining process cost, yield, and productivity for shippable chips.

[043] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode follows High-NA EUV as it moves from readiness language toward first product evidence. ASML is pointing to memory and logic products exposed within months, while imec’s quantum-dot qubit device shows how High-NA can matter beyond conventional logic and DRAM. The focus is the manufacturing loop around High-NA: masks, inspection, curvilinear data, and qualification. Key takeaways: - ASML’s CEO said first memory and logic products exposed on High-NA EUV systems should appear within months. - imec presented a quantum-dot qubit device fabricated with High-NA EUV, with barely 6-nanometer gaps between control gates. - The episode treats imec’s quantum result as a manufacturability signal, not a near-term revenue driver. - Semiconductor Engineering’s mask discussion points to inspection, repair, curvilinear qualification, and data flow as key High-NA bottlenecks. - Micron started 1-alpha DRAM manufacturing at its Manassas, Virginia fab, adding U.S. long-lifecycle memory capacity outside the EUV-heavy HBM race. - Samsung’s tentative labor deal reduced immediate strike risk, but a later court challenge kept operational uncertainty alive. - No fresh official TSMC or Rapidus update was found this week that changed the EUV outlook. - The practical High-NA question for 2026 is which product layers produce enough yield, cost, and cycle-time evidence to justify insertion. Glossary: Extreme Ultraviolet (EUV) lithography — A 13.5-nanometer exposure technology used for the most advanced semiconductor patterning layers. High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation using 0.55 NA optics for finer resolution and potentially fewer patterning steps. Low Numerical Aperture (Low-NA) EUV — Today’s 0.33 NA EUV platform, still the main production workhorse at leading fabs. Dynamic random-access memory (DRAM) — Volatile memory used in servers, personal computers, mobile devices, and high-bandwidth memory stacks. High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high bandwidth. Curvilinear mask — A photomask using curved rather than strictly rectangular features to improve imaging on difficult patterns. Inverse lithography technology (ILT) — Computational method that derives mask shapes from desired wafer patterns and process behavior. Actinic inspection — Mask inspection using EUV wavelength light to better determine whether a defect will print. Edge placement error — The deviation between intended and printed feature edges, increasingly important at advanced nodes.