[045] Deep Dive Topic - Decodes imec's new logic innovations

[045] Deep Dive Topic - Decodes imec's new logic innovations

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser This episode decodes imec's new logic innovation roadmap and explains why future scaling is no longer just about smaller transistors. We walk through the real physical metrics behind node names, the shift from FinFETs to nanosheets and CFETs, the role of High NA EUV, backside power delivery, CMOS 2.0, and active interposers. The focus is on the engineering trade-offs that make the roadmap technically credible, difficult, and important. Key takeaways - Node names are roadmap labels, not literal feature sizes. - Real scaling is better understood through contacted poly pitch, cell height, and metal pitch. - Gate-all-around nanosheets improve channel control and give designers a new drive-current versus area trade-off. - Forksheets may extend the nanosheet era, while CFETs promise tighter logic density through vertical transistor stacking. - High NA EUV improves imaging resolution but requires a new optical, mechanical, mask, and process ecosystem. - Backside power delivery attacks routing congestion and voltage loss by moving power wiring to the wafer backside. - CMOS 2.0 reframes scaling as a three-dimensional system-partitioning problem. - Active interposers could bring memory, photonics, capacitance, and voltage regulation closer to compute. - The future logic roadmap depends on co-optimizing devices, lithography, interconnect, power, packaging, and design tools. Glossary Contacted poly pitch: A physical spacing metric related to the distance between neighboring transistor gates in a standard logic cell. Cell height: The vertical size of a standard logic cell, often expressed in routing tracks. Reducing it improves density but constrains wiring and power resources. Metal pitch: The center-to-center distance between neighboring metal interconnect wires. It strongly affects wiring density and signal delay. FinFET: A fin-shaped field-effect transistor in which the gate controls multiple sides of a raised silicon channel. Gate-all-around transistor: A transistor architecture where the gate surrounds the channel on all sides for stronger electrostatic control. Nanosheet transistor: A gate-all-around transistor using stacked horizontal sheet-like channels. CFET: Complementary field-effect transistor. A future transistor architecture that vertically stacks n-type and p-type devices to reduce standard-cell footprint. High NA EUV: High numerical aperture extreme ultraviolet lithography. A next-generation EUV platform intended to print smaller features with improved resolution. Backside power delivery: A chip architecture that routes power from the wafer backside rather than through the frontside signal wiring stack. CMOS 2.0: Imec's concept for partitioning a system-on-chip into optimized functional tiers connected by dense 3D interconnects. Source list Always Be Curious, “Decoding imec's new industry roadmap for Logic innovation” — https://alwaysbecurious.substack.com/p/decoding-imecs-new-industry-roadmap

[044] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV lithography as a coordination problem rather than a single-tool problem. Korea’s approval reform, TSMC’s High-NA cost caution, SK hynix’s wafer-capacity plan, and Rapidus’s fresh government-backed funding all point to the same theme: the industry is trying to turn scarce exposure capacity into usable output faster. The focus topic connects scanner economics with regulation, memory, bonding, research speed, and system-level workarounds. Key takeaways: - South Korea plans to shorten EUV equipment import inspection and approval from 34 days to as few as nine days. - The Korean reform could cut overseas pressure and leak-test fees by about 5 billion won per EUV tool. - TSMC says it has purchased High-NA EUV tools for R&D but does not currently need them for production because the cost remains high. - SK hynix aims to double wafer capacity over the next five years while still expecting memory bottlenecks to persist into 2030. - Rapidus completed an additional 150 billion yen funding round from Japan’s Information-Technology Promotion Agency. - Intel says its 14A PDK 0.5 is available and that 14A PDK 0.9 is targeted for external customers in October. - Imec and EV Group demonstrated wafer-to-wafer hybrid bonding at a 200-nanometer copper pad pitch with post-bond overlay below 40 nanometers. - The University of Texas at Austin described a tabletop EUV and volumetric 3D patterning approach aimed at speeding research experiments, not replacing production scanners. - No new official ASML scanner shipment or throughput announcement was found this week; the ASML share buyback notice was financial housekeeping rather than a capacity update. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5-nanometer light to pattern critical layers in advanced chips. High Numerical Aperture (High-NA) EUV — next-generation EUV optics with higher resolution but higher cost and integration complexity. Low Numerical Aperture (Low-NA) EUV — today’s production EUV platform used widely for leading-edge logic and advanced memory. Process Design Kit (PDK) — the design-rule and model package customers need to begin designing chips for a foundry process. High Bandwidth Memory (HBM) — stacked DRAM used near AI processors to provide very high memory bandwidth. Dynamic Random-Access Memory (DRAM) — volatile memory technology used in servers, PCs, phones, and HBM stacks. Hybrid bonding — direct wafer or die bonding that creates dense vertical electrical connections for advanced packaging. Post-bond overlay — alignment accuracy after two wafers or dies are bonded. Cost per good die — the economic metric combining process cost, yield, and productivity for shippable chips.

[043] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode follows High-NA EUV as it moves from readiness language toward first product evidence. ASML is pointing to memory and logic products exposed within months, while imec’s quantum-dot qubit device shows how High-NA can matter beyond conventional logic and DRAM. The focus is the manufacturing loop around High-NA: masks, inspection, curvilinear data, and qualification. Key takeaways: - ASML’s CEO said first memory and logic products exposed on High-NA EUV systems should appear within months. - imec presented a quantum-dot qubit device fabricated with High-NA EUV, with barely 6-nanometer gaps between control gates. - The episode treats imec’s quantum result as a manufacturability signal, not a near-term revenue driver. - Semiconductor Engineering’s mask discussion points to inspection, repair, curvilinear qualification, and data flow as key High-NA bottlenecks. - Micron started 1-alpha DRAM manufacturing at its Manassas, Virginia fab, adding U.S. long-lifecycle memory capacity outside the EUV-heavy HBM race. - Samsung’s tentative labor deal reduced immediate strike risk, but a later court challenge kept operational uncertainty alive. - No fresh official TSMC or Rapidus update was found this week that changed the EUV outlook. - The practical High-NA question for 2026 is which product layers produce enough yield, cost, and cycle-time evidence to justify insertion. Glossary: Extreme Ultraviolet (EUV) lithography — A 13.5-nanometer exposure technology used for the most advanced semiconductor patterning layers. High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation using 0.55 NA optics for finer resolution and potentially fewer patterning steps. Low Numerical Aperture (Low-NA) EUV — Today’s 0.33 NA EUV platform, still the main production workhorse at leading fabs. Dynamic random-access memory (DRAM) — Volatile memory used in servers, personal computers, mobile devices, and high-bandwidth memory stacks. High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high bandwidth. Curvilinear mask — A photomask using curved rather than strictly rectangular features to improve imaging on difficult patterns. Inverse lithography technology (ILT) — Computational method that derives mask shapes from desired wafer patterns and process behavior. Actinic inspection — Mask inspection using EUV wavelength light to better determine whether a defect will print. Edge placement error — The deviation between intended and printed feature edges, increasingly important at advanced nodes.

[042] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode frames EUV through geography, serviceability, and industrial replication rather than a new scanner milestone. Tata Electronics and ASML put India’s first commercial 300-millimeter fab into the lithography conversation, while TSMC’s board authorizations and the MATCH Act dispute show why capacity now depends on facilities, field support, policy, and trusted regional execution. Key takeaways: - Tata Electronics and ASML signed an MoU to support the ramp of Tata’s Dholera 300-millimeter fab in Gujarat. - Tata’s disclosed Dholera portfolio spans 28nm, 40nm, 55nm, 90nm, and 110nm, making the project mainly DUV-centered rather than an EUV-frontier fab. - TSMC approved about US$31.284 billion in capital appropriations for advanced technology capacity and fab/facility systems. - TSMC also approved a capital injection of up to US$20 billion into TSMC Arizona. - Dutch objections to the proposed U.S. MATCH Act make servicing, spares, and extraterritorial export controls a live lithography-capacity issue. - China also criticized the MATCH Act, reinforcing that chip-equipment policy is becoming an operating-risk variable. - TSMC reportedly raised its 2030 global semiconductor market view to about US$1.5 trillion, with AI as the demand engine. - Apple-Intel foundry speculation is treated as background this week because the preliminary deal was already covered and no official node or product scope has changed. - No major new EUV scanner shipment or High-NA insertion datapoint was found this week, so the episode focuses on geographic replication and service infrastructure. Glossary: Extreme Ultraviolet (EUV) lithography — 13.5-nanometer wavelength lithography used for critical layers in leading-edge logic and advanced memory. Deep Ultraviolet (DUV) lithography — Earlier-generation optical lithography still essential for mature nodes and many non-critical layers in advanced flows. High Numerical Aperture (High-NA) EUV — Next-generation EUV platform with higher resolution but different economics, field-size constraints, and integration challenges. 300-millimeter fab — Semiconductor wafer fab using 12-inch wafers, the standard format for high-volume modern chip manufacturing. Memorandum of Understanding (MoU) — A formal cooperation framework that may precede detailed contracts or tool orders. Capital appropriation — Board authorization to allocate capital for capacity, construction, facility systems, or related investments. Field service — Maintenance, parts, calibration, and engineering support needed to keep tools productive after installation. MATCH Act — Proposed U.S. legislation aimed at tightening semiconductor manufacturing equipment controls involving China and allied countries. Tool availability — The share of time a manufacturing tool is operational and usable for production work.

[041] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV less as a single-tool story and more as a capacity, customer, and capital-allocation story. Apple’s reported Intel and Samsung outreach, Samsung’s 2nm foundry push, SK Hynix customer-financing talks, and TSMC’s low-NA roadmap strategy all point to the same conclusion: the bottleneck is now economic and geopolitical as much as technical. Key takeaways: - Previous scripts or sources were not available in the workspace, so non-repetition was handled on a best-effort basis. - Reuters relayed a Wall Street Journal report that Apple and Intel reached a preliminary chip-making deal, but Intel and Apple declined comment and the product scope remains unclear. - Reuters also relayed Bloomberg reporting that Apple explored U.S. chipmaking with Intel and Samsung, while Reuters could not independently verify the report. - Samsung reported Q1 2026 consolidated revenue of KRW 133.9 trillion and operating profit of KRW 57.2 trillion. - Samsung said its foundry business plans full utilization of advanced-node lines in Q2 2026, broader 2nm customer engagement, and second-generation 2nm mobile ramp in H2 2026. - Reuters reported that Samsung expects more advanced 2nm logic customers and is reviewing a second Taylor, Texas fab while targeting first Taylor volume production in 2027. - Reuters reported that SK Hynix customers have proposed funding production lines and ASML EUV tools, reflecting extreme tightness in AI-driven memory supply. - TSMC introduced A13, A12, and N2U, with N2U planned for 2028 and A13/A12 planned for 2029, while continuing to extract gains from existing EUV platforms. - ASML reported Q1 2026 net sales of €8.8 billion and updated 2026 net sales guidance to €36 billion–€40 billion. - Apple A20 and C2 modem items remain rumors; they were used only as directional signals for custom-silicon and packaging demand. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5 nm light to pattern the most critical layers in advanced chips. High Numerical Aperture (High-NA) EUV — ASML’s newer 0.55 NA EUV platform designed for finer resolution and future sub-2nm logic and advanced memory. Low numerical aperture (low-NA) EUV — the 0.33 NA EUV platform widely used for current leading-edge logic and memory production. Hyper-NA — a possible future EUV generation above High-NA, still more of a 2030s feasibility topic than a near-term production tool. 2nm — an advanced process-node class using nanosheet or gate-all-around transistor structures, with naming varying by foundry. Wafer-Level Multi-Chip Module (WMCM) — a packaging approach that integrates components at wafer level before singulation. High-Bandwidth Memory (HBM) — stacked DRAM used beside AI accelerators to provide very high data bandwidth. CoWoS — TSMC’s Chip-on-Wafer-on-Substrate advanced packaging family for large AI and high-performance computing packages. Backside power delivery — a routing approach that moves power delivery to the wafer backside to reduce congestion and improve performance. Foundry — a manufacturer that produces chips designed by external customers.