EUV The Focal Point

[042] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode frames EUV through geography, serviceability, and industrial replication rather than a new scanner milestone. Tata Electronics and ASML put India’s first commercial 300-millimeter fab into the lithography conversation, while TSMC’s board authorizations and the MATCH Act dispute show why capacity now depends on facilities, field support, policy, and trusted regional execution. Key takeaways: - Tata Electronics and ASML signed an MoU to support the ramp of Tata’s Dholera 300-millimeter fab in Gujarat. - Tata’s disclosed Dholera portfolio spans 28nm, 40nm, 55nm, 90nm, and 110nm, making the project mainly DUV-centered rather than an EUV-frontier fab. - TSMC approved about US$31.284 billion in capital appropriations for advanced technology capacity and fab/facility systems. - TSMC also approved a capital injection of up to US$20 billion into TSMC Arizona. - Dutch objections to the proposed U.S. MATCH Act make servicing, spares, and extraterritorial export controls a live lithography-capacity issue. - China also criticized the MATCH Act, reinforcing that chip-equipment policy is becoming an operating-risk variable. - TSMC reportedly raised its 2030 global semiconductor market view to about US$1.5 trillion, with AI as the demand engine. - Apple-Intel foundry speculation is treated as background this week because the preliminary deal was already covered and no official node or product scope has changed. - No major new EUV scanner shipment or High-NA insertion datapoint was found this week, so the episode focuses on geographic replication and service infrastructure. Glossary: Extreme Ultraviolet (EUV) lithography — 13.5-nanometer wavelength lithography used for critical layers in leading-edge logic and advanced memory. Deep Ultraviolet (DUV) lithography — Earlier-generation optical lithography still essential for mature nodes and many non-critical layers in advanced flows. High Numerical Aperture (High-NA) EUV — Next-generation EUV platform with higher resolution but different economics, field-size constraints, and integration challenges. 300-millimeter fab — Semiconductor wafer fab using 12-inch wafers, the standard format for high-volume modern chip manufacturing. Memorandum of Understanding (MoU) — A formal cooperation framework that may precede detailed contracts or tool orders. Capital appropriation — Board authorization to allocate capital for capacity, construction, facility systems, or related investments. Field service — Maintenance, parts, calibration, and engineering support needed to keep tools productive after installation. MATCH Act — Proposed U.S. legislation aimed at tightening semiconductor manufacturing equipment controls involving China and allied countries. Tool availability — The share of time a manufacturing tool is operational and usable for production work.

[041] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at EUV less as a single-tool story and more as a capacity, customer, and capital-allocation story. Apple’s reported Intel and Samsung outreach, Samsung’s 2nm foundry push, SK Hynix customer-financing talks, and TSMC’s low-NA roadmap strategy all point to the same conclusion: the bottleneck is now economic and geopolitical as much as technical. Key takeaways: - Previous scripts or sources were not available in the workspace, so non-repetition was handled on a best-effort basis. - Reuters relayed a Wall Street Journal report that Apple and Intel reached a preliminary chip-making deal, but Intel and Apple declined comment and the product scope remains unclear. - Reuters also relayed Bloomberg reporting that Apple explored U.S. chipmaking with Intel and Samsung, while Reuters could not independently verify the report. - Samsung reported Q1 2026 consolidated revenue of KRW 133.9 trillion and operating profit of KRW 57.2 trillion. - Samsung said its foundry business plans full utilization of advanced-node lines in Q2 2026, broader 2nm customer engagement, and second-generation 2nm mobile ramp in H2 2026. - Reuters reported that Samsung expects more advanced 2nm logic customers and is reviewing a second Taylor, Texas fab while targeting first Taylor volume production in 2027. - Reuters reported that SK Hynix customers have proposed funding production lines and ASML EUV tools, reflecting extreme tightness in AI-driven memory supply. - TSMC introduced A13, A12, and N2U, with N2U planned for 2028 and A13/A12 planned for 2029, while continuing to extract gains from existing EUV platforms. - ASML reported Q1 2026 net sales of €8.8 billion and updated 2026 net sales guidance to €36 billion–€40 billion. - Apple A20 and C2 modem items remain rumors; they were used only as directional signals for custom-silicon and packaging demand. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5 nm light to pattern the most critical layers in advanced chips. High Numerical Aperture (High-NA) EUV — ASML’s newer 0.55 NA EUV platform designed for finer resolution and future sub-2nm logic and advanced memory. Low numerical aperture (low-NA) EUV — the 0.33 NA EUV platform widely used for current leading-edge logic and memory production. Hyper-NA — a possible future EUV generation above High-NA, still more of a 2030s feasibility topic than a near-term production tool. 2nm — an advanced process-node class using nanosheet or gate-all-around transistor structures, with naming varying by foundry. Wafer-Level Multi-Chip Module (WMCM) — a packaging approach that integrates components at wafer level before singulation. High-Bandwidth Memory (HBM) — stacked DRAM used beside AI accelerators to provide very high data bandwidth. CoWoS — TSMC’s Chip-on-Wafer-on-Substrate advanced packaging family for large AI and high-performance computing packages. Backside power delivery — a routing approach that moves power delivery to the wafer backside to reduce congestion and improve performance. Foundry — a manufacturer that produces chips designed by external customers.

[040] Deep Dive Topic - Advanced Packaging

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser Advanced packaging has become one of the decisive technologies behind EUV-era semiconductors. This episode explains how modern packages connect chiplets, high-bandwidth memory, substrates, and cooling into one working system. It also maps the key players across foundries, integrated device manufacturers, OSATs, memory suppliers, substrates, materials, and equipment. Key takeaways - Advanced packaging is not EUV lithography itself. It is the system-level integration technology that makes EUV-era chips usable in real products. - A package is no longer just protection. In high-end computing, it is an electrical, thermal, mechanical, and architectural platform. - Fan-out packaging redistributes chip connections beyond the die outline using molded reconstituted wafers or panels and copper redistribution layers. - Two point five D packaging places logic and memory side by side on a high-density interposer or bridge to increase bandwidth. - Three D packaging stacks active dies vertically to shorten connections, but it makes heat removal, power delivery, testing, and yield harder. - Hybrid bonding removes conventional solder bumps and enables much denser die-to-die connections through direct copper and dielectric bonding. - High-bandwidth memory is a central driver of advanced packaging demand for AI accelerators. - TSMC, Samsung, and Intel are central high-end platform players; ASE, Amkor, and JCET are major OSAT players. - SK Hynix, Samsung, and Micron matter because advanced memory packaging is tightly linked to AI system performance. - Substrate, material, and equipment suppliers such as Ibiden, Unimicron, Shinko Electric, AT&S, Samsung Electro-Mechanics, Ajinomoto, BESI, EV Group, Applied Materials, Tokyo Electron, and ASMPT form the hidden backbone of the ecosystem. Glossary - EUV: Extreme ultraviolet lithography, a front-end chipmaking method used to print very small features in advanced semiconductor processes. - Advanced packaging: High-density semiconductor assembly and integration methods that connect multiple dies, memory stacks, substrates, and thermal structures. - Chiplet: A smaller functional die designed to be combined with other dies inside one package. - Fan-out packaging: A wafer-level or panel-level method that embeds dies and builds redistribution layers to route connections beyond the original die area. - Interposer: A high-density routing layer between dies and the package substrate, often made from silicon, organic materials, or redistribution-layer structures. - Through-silicon via: A vertical metal connection through silicon that carries signals or power between layers. - Hybrid bonding: A bonding method that joins dielectric surfaces and copper pads directly, enabling very dense vertical interconnects. - HBM: High-bandwidth memory, a stacked memory technology placed close to processors for very wide, fast data movement. - OSAT: Outsourced semiconductor assembly and test provider; a company that packages and tests chips for other semiconductor firms. - ABF substrate: A high-performance build-up substrate technology using Ajinomoto Build-up Film as an insulating material.

[039] Industry briefing - EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode is a light scanner-shipment week, but a strong roadmap and economics week. The central theme is coexistence: DUV, Low-NA EUV, High-NA EUV, and advanced packaging are becoming complementary tools rather than sequential replacements. The episode looks at TSMC’s A16 timing, Samsung’s record chip results, Big Tech’s AI spending pressure, and why ASML’s workhorse Low-NA fleet still matters. Key takeaways: - TSMC’s A16 is described as ready for production in 2026, but volume production is now aligned to 2027 because customer ramp timing drives the schedule. - TSMC’s A12 and A13 roadmap through 2029 continues to avoid High-NA EUV, reinforcing a strategy of extending current Low-NA EUV capability. - TrendForce frames TSMC’s High-NA deferral as a Low-NA strength story rather than a near-term collapse in EUV demand. - ASML’s near-term EUV economics remain tied to Low-NA output and upgrades, including at least 60 Low-NA EUV systems in 2026 and a path toward about 80 in 2027. - Samsung reported KRW 133.9 trillion in Q1 revenue and KRW 57.2 trillion in operating profit, with its Device Solutions division contributing KRW 53.7 trillion of operating profit. - Samsung said it started mass product sales of HBM4 and SOCAMM2 for NVIDIA’s Vera Rubin platform and plans first HBM4E samples in Q2 2026. - Reuters Breakingviews reported that Alphabet, Amazon, Meta, and Microsoft may invest up to $725 billion this year, while Alphabet said cloud revenue was limited by processor constraints. - TSMC’s SoIC roadmap points from 6-micron hybrid-bonding pitch in 2025 toward 4.5 microns in 2029, showing that packaging is increasingly part of the scaling answer. - No major new official ASML scanner shipment announcement surfaced this week; the episode therefore emphasizes roadmap timing, customer adoption, and cost-per-good-die logic. Glossary: EUV — Extreme Ultraviolet lithography, the 13.5-nanometer exposure technology used for the most critical layers in advanced chips. Low-NA EUV — Current-generation EUV lithography using a 0.33 numerical aperture optical system. High-NA EUV — Next-generation EUV lithography using a 0.55 numerical aperture system for finer patterning on selected critical layers. DUV — Deep Ultraviolet lithography, still used for many layers even in advanced chips. A16 — TSMC’s data-center-oriented node family using Super Power Rail backside power delivery. Backside power delivery — A power-routing approach that moves power rails to the back of the wafer to improve routing and power integrity. HBM4 — Fourth-generation High Bandwidth Memory for AI accelerators and high-performance computing systems. SoIC — TSMC’s System on Integrated Chips 3D stacking technology using hybrid bonding for vertical die-to-die connections. CoWoS — TSMC’s Chip on Wafer on Substrate advanced packaging platform for large AI and HPC packages. Cost per good die — The manufacturing cost of each functional die after yield, cycle time, tool cost, and process complexity are included.

[038] Deep Dive Topic - Reticles

This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser This episode explains why EUV reticles are much more than chip-pattern stencils. We unpack how reflective multilayer masks work, why buried defects and mask three-dimensional effects matter, how pellicles and actinic inspection protect yield, and why reticles are central to the economics of advanced semiconductor manufacturing. We also look at what High-NA EUV changes for future reticle design, testing, and infrastructure. Key takeaways - EUV reticles are reflective multilayer optical components, not transparent masks. - The core EUV mask stack includes a low thermal expansion substrate, a molybdenum/silicon multilayer mirror, a capping layer, and a patterned absorber. - Buried multilayer defects can be printable because they can disturb the reflected EUV wavefront. - Mask three-dimensional effects arise because EUV light sees the absorber topography at an oblique angle. - Pellicles reduce particle risk, but they add EUV transmission, heating, lifetime, inspection, and cost trade-offs. - Actinic inspection uses EUV light to judge whether a mask defect is likely to print on the wafer. - Reticle economics include not only the mask itself, but also blanks, writing, inspection, repair, cleaning, pellicles, storage, and re-spin risk. - High-NA EUV makes reticle strategy more complex through anamorphic imaging, half-field exposure, possible stitching, and possible future larger mask formats. Glossary - EUV lithography: Extreme ultraviolet lithography, a chip patterning method using light near thirteen point five nanometers. - Reticle: The master mask carrying the circuit pattern for one lithography layer. - Mask blank: The unpatterned reticle substrate and optical stack before the circuit pattern is written. - Multilayer mirror: Alternating nanometer-scale layers that reflect EUV light by constructive interference. - Absorber: The patterned layer that reduces EUV reflection in dark regions of the mask. - Mask three-dimensional effects: Imaging errors caused by the real height, shape, and material properties of mask features. - Pellicle: A thin protective membrane that keeps particles away from the reticle surface. - Actinic inspection: Inspection using the same wavelength as the lithography exposure. - Aerial image review: Mask qualification that checks how a defect or repair appears under scanner-like imaging conditions. - High-NA EUV: Next-generation EUV lithography using higher numerical aperture optics for improved resolution.